Packaging Developments From ECTC 2022 – TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony’s Leading 1-Micron Pitch Hybrid Bonding, MediaTek Networking SoC, Co-Packaged Optics, And More

TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony’s Leading 1-Micron Pitch Hybrid Bonding, MediaTek Networking SoC, and Co-Packaged Optics

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Is Ampere Computing’s Cloud Native Marketing Fluff? – Siryn Ampere One 5nm Architecture, Cost Analysis, and IPO Analysis

We break through the marketing fluff of Ampere. We also did a cost comparison of Ampere’s Altra and Altra Max to AMD Milan and Intel Icelake. We also do a similar comparison with projected specs for the 5nm based Siryn. SemiAnalysis also details the architecture, including architecture diagrams, on Ampere One exclusively with the help of Cardyak,

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Advanced Packaging Part 2 – Review Of Options/Use From Intel, TSMC, Samsung, AMD, ASE, Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia

Advanced packaging exists on a continuum of cost and throughput vs performance and density. Even though the demand for advanced packaging is obvious, there is an incredible number of advanced packaging types and brand names from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS­-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/LPDDR DRAM, CIS), ASE (FoCoS, FOEB), Sony (CIS), Micron (HBM), SKHynix (HBM), and YMTC (XStacking). These packaging types are used by all of our favorite companies from AMD, Nvidia, and many more. In Part 2, we will explain all these types of packaging and their uses.

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TSMC Wants To Make Intel Dependent On External Manufacturing – Wafer Supply Agreement Insights For AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm

People all over semiconductor world have been speculating about the TSMC and Intel deal. SemiAnalysis wants to set the record straight on these. We are going to dive into the details for wafer supply agreements including prepayment terms and capacity agreements for AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm.

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Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets

In this multi-part series we will do a deep dive into the advanced packaging mega-trend. This will include a breakdown of the various types of advanced packaging, flows, tool types, and vendors. In part 1 we dive into what pad limited designs are, the slowdown of Moore’s Law and end of economic shrinks, heterogeneous compute, and the economic and design implications of chiplets.

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Amazon Graviton 3 Uses Chiplets & Advanced Packaging To Commoditize High Performance CPUs | The First PCIe 5.0 And DDR5 Server CPU

Shots are being fired at merchant silicon.
Amazon’s Graviton3 completely commoditizes generalized CPU compute while also bringing advanced packaging, PCIe 5.0, and DDR5 to the server market ~6 months before Intel and AMD.
Server and rack level system architecture choices propel Graviton 3 to new heights in cost per unit of compute.
There’s something special about the packaging behind the paywall.

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