AMD – SemiAnalysis

Advanced Packaging Part 2 – Review Of Options/Use From Intel, TSMC, Samsung, AMD, ASE, Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia

January 6, 2022January 19, 2022 Dylan Patel 0 Comments CoWoS-L, CoWoS-S, CoWoS-R, EMIB, FoCoS, FOEB, FOSiP, Foveros, Foveros Direct, Foveros Omni, HBM, I-Cube, InFO-LSI, InFO-OS, InFO-SoIS, InFO-SOW, SoIC, X-Cube, XStacking

Advanced packaging exists on a continuum of cost and throughput vs performance and density. Even though the demand for advanced packaging is obvious, there is an incredible number of advanced packaging types and brand names from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/LPDDR DRAM, CIS), ASE (FoCoS, FOEB), Sony (CIS), Micron (HBM), SKHynix (HBM), and YMTC (XStacking). These packaging types are used by all of our favorite companies from AMD, Nvidia, and many more. In Part 2, we will explain all these types of packaging and their uses.

AMD Apple Broadcom Intel Logic MediaTek Nvidia Qualcomm

TSMC Wants To Make Intel Dependent On External Manufacturing – Wafer Supply Agreement Insights For AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm

December 22, 2021December 27, 2021 Dylan Patel 0 Comments Intel 20A, Intel 4, Intel 7, Long Term Supply Agreements, N3, N3E, N4, N4P, N5, N5P, N6, N7, Pre-Paid Capacity, Wafer Supply Agreement

People all over semiconductor world have been speculating about the TSMC and Intel deal. SemiAnalysis wants to set the record straight on these. We are going to dive into the details for wafer supply agreements including prepayment terms and capacity agreements for AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm.

AMD Apple Intel KLIC Logic Mobile Nvidia Packaging TSMC

Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets

December 15, 2021January 19, 2022 Dylan Patel 0 Comments Advanced Packaging, chiplets, CoWoS, EMIB, Fan Out, heterogeneous compute, InFO, pad limited, process node, SRAM, TSV, vcache

In this multi-part series we will do a deep dive into the advanced packaging mega-trend. This will include a breakdown of the various types of advanced packaging, flows, tool types, and vendors. In part 1 we dive into what pad limited designs are, the slowdown of Moore’s Law and end of economic shrinks, heterogeneous compute, and the economic and design implications of chiplets.

Amazon AMD Arm Intel Logic

Amazon Graviton 3 Uses Chiplets & Advanced Packaging To Commoditize High Performance CPUs | The First PCIe 5.0 And DDR5 Server CPU

December 2, 2021December 7, 2021 Dylan Patel 6 Comments Amazon, AMD, AWS, AWS EBS, AWS Elastic Block Storage., AWS Nitro, DDR5, Graviton 2, Graviton 3, Graviton2, Graviton3, Intel, Neoverse N1, Neoverse N2, Neoverse V1, Nitro, PCIe 5.0

Shots are being fired at merchant silicon.
Amazon’s Graviton3 completely commoditizes generalized CPU compute while also bringing advanced packaging, PCIe 5.0, and DDR5 to the server market ~6 months before Intel and AMD.
Server and rack level system architecture choices propel Graviton 3 to new heights in cost per unit of compute.
There’s something special about the packaging behind the paywall.