Advanced Packaging Part 3 – Intel’s Curious Bet on Thermocompression Bonding, ASM Pacific, Kulicke and Soffa, and Besi TCB Tool Landscape

Intel co-developed a thermocompression bonding tool which they own hundreds of. TCB is a key enabler in their advanced packaging strategy and a key differentiator versus their competition such as TSMC on a cost and integration basis.

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Advanced Packaging Part 2 – Review Of Options/Use From Intel, TSMC, Samsung, AMD, ASE, Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia

Advanced packaging exists on a continuum of cost and throughput vs performance and density. Even though the demand for advanced packaging is obvious, there is an incredible number of advanced packaging types and brand names from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS­-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/LPDDR DRAM, CIS), ASE (FoCoS, FOEB), Sony (CIS), Micron (HBM), SKHynix (HBM), and YMTC (XStacking). These packaging types are used by all of our favorite companies from AMD, Nvidia, and many more. In Part 2, we will explain all these types of packaging and their uses.

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TSMC Wants To Make Intel Dependent On External Manufacturing – Wafer Supply Agreement Insights For AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm

People all over semiconductor world have been speculating about the TSMC and Intel deal. SemiAnalysis wants to set the record straight on these. We are going to dive into the details for wafer supply agreements including prepayment terms and capacity agreements for AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm.

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Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets

In this multi-part series we will do a deep dive into the advanced packaging mega-trend. This will include a breakdown of the various types of advanced packaging, flows, tool types, and vendors. In part 1 we dive into what pad limited designs are, the slowdown of Moore’s Law and end of economic shrinks, heterogeneous compute, and the economic and design implications of chiplets.

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Amazon Graviton 3 Uses Chiplets & Advanced Packaging To Commoditize High Performance CPUs | The First PCIe 5.0 And DDR5 Server CPU

Shots are being fired at merchant silicon.
Amazon’s Graviton3 completely commoditizes generalized CPU compute while also bringing advanced packaging, PCIe 5.0, and DDR5 to the server market ~6 months before Intel and AMD.
Server and rack level system architecture choices propel Graviton 3 to new heights in cost per unit of compute.
There’s something special about the packaging behind the paywall.

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Intel Betting The Farm – Shrinking Business, Margins Down For Few Years, But Aggressively Investing $40B-$43B A Year And More With Subsidies

Intel could follow the path of many other American goliaths such as IBM and General Electric. A slow slide to irrelevancy, spinning off business, and bringing shame to what was once pride for American ingenuity. Instead of that conservative route, they are going to put the metal to the floor, spend every dime Intel makes on investing in more manufacturing, design, and in general catching up in technology.

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TSMC 3nm Wafer Shipments Pushed Into Q1 2023, 2.5 Years After N5 | TSMC 2nm, Samsung 2nm, And Intel 20A Battle It Out In 2025

SemiAnalysis has been hearing murmurings about TSMC’s N3 having poor yields, poor metal stack performance, being very expensive, and being too late for Apple’s 2022 iPhone. These can’t be confirmed, but we can confirm that TSMC N3 is now shipping in Q1 2023.
The hiccup on N3 brings many questions about TSMC’s competitive positioning versus Intel 20A and Samsung 2nm. Both these nodes are very aggressive and aimed at getting back into a competitive position against TSMC. Intel and Samsung even claim the nodes will bring leadership.

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Aehr Multi-Wafer Level Burn-in Test for Silicon Carbide and Silicon Photonics Applications

Test intensity for silicon carbide and photonics is very high due to extreme operating ranges. Wafer level burn in could transform the test life cycle for semiconductors. Major wins such as On Semiconductor and Intel validate this.

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