GlobalFoundries Fotonix, The Leading Silicon Photonics Foundry For Co-packaged Optics And Processing – Wins At Nvidia, Broadcom, Marvell, Cisco, Macom, Ayar Labs, Lightmatter, PsiQuantum, Ranovus, And Xanadu

They have numerous wins at Nvidia, Broadcom, Marvell, Cisco, Macom, Ayar Labs, Lightmatter, PsiQuantum, Ranovus, And Xanadu. In addition they are deeply integrated with the PDK and simulation toolchain with partnerships with Ansys, Cadence, and Synopsys.

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Advanced Packaging Part 2 – Review Of Options/Use From Intel, TSMC, Samsung, AMD, ASE, Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia

Advanced packaging exists on a continuum of cost and throughput vs performance and density. Even though the demand for advanced packaging is obvious, there is an incredible number of advanced packaging types and brand names from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS­-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/LPDDR DRAM, CIS), ASE (FoCoS, FOEB), Sony (CIS), Micron (HBM), SKHynix (HBM), and YMTC (XStacking). These packaging types are used by all of our favorite companies from AMD, Nvidia, and many more. In Part 2, we will explain all these types of packaging and their uses.

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TSMC Wants To Make Intel Dependent On External Manufacturing – Wafer Supply Agreement Insights For AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm

People all over semiconductor world have been speculating about the TSMC and Intel deal. SemiAnalysis wants to set the record straight on these. We are going to dive into the details for wafer supply agreements including prepayment terms and capacity agreements for AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm.

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Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets

In this multi-part series we will do a deep dive into the advanced packaging mega-trend. This will include a breakdown of the various types of advanced packaging, flows, tool types, and vendors. In part 1 we dive into what pad limited designs are, the slowdown of Moore’s Law and end of economic shrinks, heterogeneous compute, and the economic and design implications of chiplets.

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Tesla Dojo – Unique Packaging and Chip Design Allow An Order Magnitude Advantage Over Competing AI Hardware

Tesla has flipped the hardware world on its head by creating a chip with GPU levels of compute, more than the highest end networking chips IO, and high levels of flexibility. They utilize a integrated fan out system on wafer that achieves better scale up and scale out performance than Nvidia, Graphcore, Cerebras, Groq, Tenstorrent, SambaNova, or any other AI training startup.

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