Packaging Developments From ECTC 2022 – TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony’s Leading 1-Micron Pitch Hybrid Bonding, MediaTek Networking SoC, Co-Packaged Optics, And More

TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony’s Leading 1-Micron Pitch Hybrid Bonding, MediaTek Networking SoC, and Co-Packaged Optics

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Semiconductor Roundup – GlobalFoundries, Sumco, GlobalWafers, Power Integrations, FormFactor, Texas Instruments, Ichor, Ford, Kulicke and Soffa Industries, TSMC, Amazon, Skyworks, Qorvo, Qualcomm, Murata, Rambus, and Renesas – 2/10/2022

GlobalFoundries, Sumco, GlobalWafers, Power Integrations, FormFactor, Texas Instruments, Ichor, Ford, Kulicke and Soffa Industries, TSMC, Amazon, Skyworks, Qorvo, Qualcomm, Murata, Rambus, and Renesas

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TSMC Throws Down a $40B-$44B Gauntlet, Far Surpassing Intel And Samsung

TSMC is the world’s leading foundry, and they are making sure it stays that way. Intel and Samsung initiated quite ambitious plans last year that would take their spending on logic semiconductor fabs to $25B+ a year. Alongside these aggressive spending plans, Intel and Samsung pushed roadmaps that would take them to leadership performance, power, and density. TSMC puts ceiling on their ambitious plans.

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Advanced Packaging Part 2 – Review Of Options/Use From Intel, TSMC, Samsung, AMD, ASE, Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia

Advanced packaging exists on a continuum of cost and throughput vs performance and density. Even though the demand for advanced packaging is obvious, there is an incredible number of advanced packaging types and brand names from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS­-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/LPDDR DRAM, CIS), ASE (FoCoS, FOEB), Sony (CIS), Micron (HBM), SKHynix (HBM), and YMTC (XStacking). These packaging types are used by all of our favorite companies from AMD, Nvidia, and many more. In Part 2, we will explain all these types of packaging and their uses.

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Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets

In this multi-part series we will do a deep dive into the advanced packaging mega-trend. This will include a breakdown of the various types of advanced packaging, flows, tool types, and vendors. In part 1 we dive into what pad limited designs are, the slowdown of Moore’s Law and end of economic shrinks, heterogeneous compute, and the economic and design implications of chiplets.

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TSMC 3nm Wafer Shipments Pushed Into Q1 2023, 2.5 Years After N5 | TSMC 2nm, Samsung 2nm, And Intel 20A Battle It Out In 2025

SemiAnalysis has been hearing murmurings about TSMC’s N3 having poor yields, poor metal stack performance, being very expensive, and being too late for Apple’s 2022 iPhone. These can’t be confirmed, but we can confirm that TSMC N3 is now shipping in Q1 2023.
The hiccup on N3 brings many questions about TSMC’s competitive positioning versus Intel 20A and Samsung 2nm. Both these nodes are very aggressive and aimed at getting back into a competitive position against TSMC. Intel and Samsung even claim the nodes will bring leadership.

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Tesla AI Day Supercomputer Chip Teaser | Is This The First Deployment Of TSMC InFO_SoW?

Tesla is known for having their own silicon strategy for their automobiles and was rumored to be working on a AI training chip for their own datacenter use cases as well. An image of this chip was posted and it is quite bizarre. It looks like it could be the first TSMC InFO_SoW product.

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