Bridging the gap between business and the worlds most important industry.
A smaller die size isn’t always better. In fact, it can significantly increase your cost per wafer if special care isn’t give during the design process.
Read more
TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony’s Leading 1-Micron Pitch Hybrid Bonding, MediaTek Networking SoC, and Co-Packaged Optics
Read more
Deep dive on Graphcore’s Bow AI accelerator and wafer-on-wafer hybrid bonding technology including the purpose, advantages, cost, process flow, and whose semiconductor manufacturing tools are utilized
Read more
Western fabs and semiconductor capital equipment spending to go bonkers
Read more
GlobalFoundries, Sumco, GlobalWafers, Power Integrations, FormFactor, Texas Instruments, Ichor, Ford, Kulicke and Soffa Industries, TSMC, Amazon, Skyworks, Qorvo, Qualcomm, Murata, Rambus, and Renesas
Read more
TSMC is the world’s leading foundry, and they are making sure it stays that way. Intel and Samsung initiated quite ambitious plans last year that would take their spending on logic semiconductor fabs to $25B+ a year. Alongside these aggressive spending plans, Intel and Samsung pushed roadmaps that would take them to leadership performance, power, and density. TSMC puts ceiling on their ambitious plans.
Read more
Advanced packaging exists on a continuum of cost and throughput vs performance and density. Even though the demand for advanced packaging is obvious, there is an incredible number of advanced packaging types and brand names from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/LPDDR DRAM, CIS), ASE (FoCoS, FOEB), Sony (CIS), Micron (HBM), SKHynix (HBM), and YMTC (XStacking). These packaging types are used by all of our favorite companies from AMD, Nvidia, and many more. In Part 2, we will explain all these types of packaging and their uses.
Read more
In this multi-part series we will do a deep dive into the advanced packaging mega-trend. This will include a breakdown of the various types of advanced packaging, flows, tool types, and vendors. In part 1 we dive into what pad limited designs are, the slowdown of Moore’s Law and end of economic shrinks, heterogeneous compute, and the economic and design implications of chiplets.
Read more
SemiAnalysis has been hearing murmurings about TSMC’s N3 having poor yields, poor metal stack performance, being very expensive, and being too late for Apple’s 2022 iPhone. These can’t be confirmed, but we can confirm that TSMC N3 is now shipping in Q1 2023.
The hiccup on N3 brings many questions about TSMC’s competitive positioning versus Intel 20A and Samsung 2nm. Both these nodes are very aggressive and aimed at getting back into a competitive position against TSMC. Intel and Samsung even claim the nodes will bring leadership.
Tesla is known for having their own silicon strategy for their automobiles and was rumored to be working on a AI training chip for their own datacenter use cases as well. An image of this chip was posted and it is quite bizarre. It looks like it could be the first TSMC InFO_SoW product.
Read more
