Packaging Developments From ECTC 2022 – TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony’s Leading 1-Micron Pitch Hybrid Bonding, MediaTek Networking SoC, Co-Packaged Optics, And More

TSMC CoWoS-R+, TSMC 4th Generation SoIC, Intel Collective Die To Wafer Hybrid Bonding, AMD V-Cache, Sony’s Leading 1-Micron Pitch Hybrid Bonding, MediaTek Networking SoC, and Co-Packaged Optics

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Advanced Packaging Part 3 – Intel’s Curious Bet on Thermocompression Bonding, ASM Pacific, Kulicke and Soffa, and Besi TCB Tool Landscape

Intel co-developed a thermocompression bonding tool which they own hundreds of. TCB is a key enabler in their advanced packaging strategy and a key differentiator versus their competition such as TSMC on a cost and integration basis.

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Advanced Packaging Part 2 – Review Of Options/Use From Intel, TSMC, Samsung, AMD, ASE, Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia

Advanced packaging exists on a continuum of cost and throughput vs performance and density. Even though the demand for advanced packaging is obvious, there is an incredible number of advanced packaging types and brand names from Intel (EMIB, Foveros, Foveros Omni, Foveros Direct), TSMC (InFO-OS, InFO-LSI, InFO-SOW, InFO-SoIS, CoWoS-S, CoWoS­-R, CoWoS-L, SoIC), Samsung (FOSiP, X-Cube, I-Cube, HBM, DDR/LPDDR DRAM, CIS), ASE (FoCoS, FOEB), Sony (CIS), Micron (HBM), SKHynix (HBM), and YMTC (XStacking). These packaging types are used by all of our favorite companies from AMD, Nvidia, and many more. In Part 2, we will explain all these types of packaging and their uses.

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Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets

In this multi-part series we will do a deep dive into the advanced packaging mega-trend. This will include a breakdown of the various types of advanced packaging, flows, tool types, and vendors. In part 1 we dive into what pad limited designs are, the slowdown of Moore’s Law and end of economic shrinks, heterogeneous compute, and the economic and design implications of chiplets.

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Aehr Multi-Wafer Level Burn-in Test for Silicon Carbide and Silicon Photonics Applications

Test intensity for silicon carbide and photonics is very high due to extreme operating ranges. Wafer level burn in could transform the test life cycle for semiconductors. Major wins such as On Semiconductor and Intel validate this.

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Kulicke & Soffa Industries, $KLIC, Continued Outperformance Of Wire Bonders And Emerging Supplier in Mini-LED, Micro-LED, And Battery Manufacturing

Kulicke and Soffa Industries is continuing to outperform on the back of the wire bonder business. Additionally, they are emerging as a leading supplier in tools used for mini-LED, micro-LED, and battery manufacturing.

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