Intel Icelake Server Die Size & Floorplan Inefficiencies Revealed

Icelake server CPUs are set to qualify for production at the end of Q4 2020 and ramp in Q1 2021 according to Intel. As we get closer to this date, more information is being released and leaked. Intel showed a die shot of Icelake SP at HotChips 2020. The specific die shown was a 28C Ice Lake-SP die. Our understanding is that this is the HCC (High Core Count) die.

While the core count and performance come nowhere close to the competition from AMD or various ARM Server SOCs, it is an interesting image. Similar to Sky Lake SP with its LCC, HCC, and XCC dies which are differentiated primarily by core count, Intel has taped 3 dies for Ice Lake server.

The smallest of the 3 Icelake die are already sampling fairly widely. Yukki_AnS has delidded an ICX LCC die. The package measures in at 77.5mm x 56.5mm.

From leaked specs and the above image, Skyjuice was able to create floorplans of the 3 SOC variants. ICX LCC comes in at 16 cores with 2 UPI links for inter-socket communications. The other standardized IO are 8 channels DDR4 and 64 PCI 4.0 Lanes. The die measures in at 370mm2.

The middle of the stack die, ICX HCC, measures in at 28 cores. The UPI lane count is increased to 3. It retains the other IO with the same 8 channels of DDR4 and 64 PCIe 4.0 lanes. This die comes in at a whopping 505mm2.

The largest die of them all, ICX XCC, comes with 42 cores. The other IO will remain the same as the HCC die. Rumors point out that Intel will not be shipping all 42 cores enabled though. This is likely due the massive die size of 640mm2. 10nm is likely still not mature enough to yield a large monolithic die of this size. SemiAnalysis has heard that the highest end SKU will only ship at 38 cores.

With the current generation SKX, Intel uses two memory controller tiles that handle 3 channels each, giving 6 channels total for the CPU, which can be optionally split into two NUMA regions. Intel revealed at Hot Chips 21 that ICX will use 4 memory controller tiles to achieve 8ch memory for ICX, with each tile responsible for two channels. However, closer inspection of the die shows a similar memory controller layout as SKX where each tile has provisions for 3 memory channels. Hence it is somewhat interesting that there appears to be 12 channels of memory controllers on the die total, even though the LGA4189 socket can only electrically expose 8.

This is even more peculiar, given Intel’s glacial 10nm ramp. SemiAnalysis is baffled Intel would be inefficient in the layout of their large dies, wasting area around the perimeter for memory channels that will never be used. With SKX, Intel showed how they are able to optimize the layout to provide a smaller die with more cores (25c w/ untiled memory controller, 28c w/ tiled memory controller). We are not sure why ICX layout regresses in that aspect, with more wasted area outside even the memory PHYs.

Intel’s strategy of monolithic dies is a dead end one. ICX dies are so massive and XCC is already right at the reticle limit. Intel has no choice but to look at MCM for the next generation Sapphire Rapids, which is set to debut towards the end of 2021. The more complex cores and usage of the 10nm Enhanced Super Fin node means that monolithic simply cannot scale to the core counts required. Intel is believed to be moving to 2.5D EMIB integration with the next generation Sapphire Rapids and to 3D Feverous Integration with Granite Rapids.

Ice Lake Server has a marginal core count increase and higher total power draw versus the current Sky Lake and Cascade Lake Server CPUs. Due to this, SemiAnalysis believes it will be completely uncompetitive with Amazon’s Graviton 3, Nvidia’s H100, and of course, AMD’s Milan. Intel will continue to lose server market share well into 2023, and potentially beyond, given what we know of their roadmaps.

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