Accelerator & HBM Model
SKU-level tracking of AI accelerator shipments, pricing, and HBM supply, from foundry wafer starts to installed FLOPS. Used by hyperscalers, semiconductor suppliers, and institutional investors for competitive analysis, supply chain planning, and revenue modeling.
- Coverage
- 2021–2030
- Vendors covered
- 22
- SKUs tracked
- 85+
- Buyers modeled
- 60+
Accelerator production, from wafer starts to installed FLOPS.
The SemiAnalysis Accelerator & HBM Model tracks historical and future AI accelerator production by company, SKU, and quarter: how many units ship, at what price, with what specifications and memory attached, and where they end up. XPU and HBM shipment forecasts run to 2030, with supply chain, foundry, and HBM history extending back to 2021.
The model connects upstream capacity to downstream deployment. Because shipments are built up from equipment requirements, wafer starts, and packaging orders, revenue for companies across the upstream and downstream supply chain can be estimated directly from the data.
Who uses it, and what it decides.
The buyers of this model, and the calls they make with it.
- Hyperscalers & semiconductor companies
- Competitive analysis and supply chain planning: how many accelerators each rival deploys through 2030, and on which SKUs.
- Public & private market investors
- Revenue models for the names tied to accelerator production, from merchant silicon through packaging and equipment.
- Foundry, packaging & supply chain suppliers
- Capacity sizing and revenue estimation: where HBM constraints bind, how much 2.5D capacity is already spoken for, and what production data implies for their own revenue.
Five modules, one supply chain.
Each module is built from primary research and reconciled against the others, so supply, demand, and installed base stay consistent.
Accelerator shipments, ASPs & specifications
Unit shipments and ASPs for every tracked SKU, quarter by quarter, with a chip specifications reference alongside: chip family, memory type, layer count, capacity per layer and stack, HBM stack count, total memory capacity, data rate, and memory bandwidth. Chip, server, and rack-level SKUs are tracked, from HGX, SXM, and PCIe form factors to NVL36 and NVL72 rack configurations, across Western and Chinese accelerators.
- NvidiaA100, A800, H100, H200, H800, H20, H20E, B200, B300, GB200 NVL72 & NVL36, GB300 NVL72, RTX Pro 6000, Rubin, Rubin Ultra, Feynman, Feynman Ultra, Feynman Next, L40S, L20, Goq LP30, LP35, LP40, LP50Merchant
- GoogleTPU v4 Pufferfish, v4i Pufferlite, v5p Viperfish, v5e Viperlite, v6 Ghostlite, v7 Ghostfish, v8i Sunfish, v8t Zebrafish, v9, v10, v11, TIA, MeropeCustom
- AMDMI300X, MI308X, MI325X, MI350X, MI450X, MI500, MI600, MI700Merchant
- AWSTrainium 1–6, with server-type detail: Teton PD, PD Ultra, PDSCustom
- MetaMTIA 200, 300 Athena, 400 Iris+, 450 Arke, 500 Astrid, 600 OlympusCustom
- MicrosoftMaia 100, 200, 300, 400, 500Custom
- CerebrasCS-2, CS-3, CS-4, CS-5Merchant
- IntelHabana Gaudi 2, Gaudi 3, Falcon ShoresMerchant
- OpenAIGen 1, Gen 2Custom
- SoftBankIzanagiCustom
- AppleBaltra-SotraCustom
- TeslaDojo, AI4, AI5, AI6Custom
- HuaweiAscend 910B, Ascend 910CChina
- ByteDanceCustom ASICsChina
- AlibabaT-Head ZhenwuChina
- BaiduKunlunxinChina
- CambriconSiyuan 590, Siyuan 690China
- IluvatarCoreXChina
- China domesticBiren, Hygon, Enflame, MooreThreadsChina
The module also carries accelerator revenue forecasts for merchant and semi-custom providers: Nvidia, AMD, Broadcom, Marvell, Intel, Alchip, and MediaTek.
Optical engines & co-packaged optics
Shipments of TSMC COUPE optical engines tied to switch and XPU platforms, with visibility into optical attach for next-generation networking silicon:
1.6 Tbps engines
COUPE engine shipments by platform
Switch platforms
Attach across Nvidia Quantum-3 and Spectrum families
XPU platforms
Optical attach mapped to accelerator platforms
Supply chain & capacity orders
Capacity orders for every tracked chip, resolved to the physical steps that gate production:
Foundry wafers
Wafer counts by chip and quarter, broken out by process node (TSMC N7, N6, N5, N3 families) and by foundry
2.5D & advanced packaging
Wafer counts, package sizes, gross die per wafer, and yields across TSMC, Samsung, Intel, Amkor, and ASE SPIL, with CoWoS technology and merchant-versus-ASIC splits
Die attach
Total die attach steps across BESI, ASMPT, and peers
ODM & rack builds
L10 rack-build tracking by ODM, such as Quanta, and by customer, such as Meta and Microsoft
Capacity order data carries direct implications for upstream fabrication, packaging, and equipment demand.
HBM & memory
HBM is the binding constraint for most of the accelerators above, so the model tracks the memory build in the same detail as the compute:
- HBM type & generation
- Total capacity
- Layer count
- Stacks per package
- Total bits
- Manufacturer
HBM pricing
Reference ASPs and pricing tiers by supplier, customer, generation, and layer count
Supply by chip
Stacks and capacity mapped to each accelerator SKU
Memory vendor detail
Wafer starts, core-die wafers, process node, and gross core die per wafer for SK hynix, Samsung, and Micron
Customer-level installed base
Shipments and installed base for every major buyer we track, across four groups:
- US and Chinese hyperscalers
- Enterprises
- Neoclouds such as CoreWeave
- Startups and sovereign AI programs
Installed base converts to compute: peak theoretical FLOPS and effective FLOPS, derived from training Model FLOPs Utilization (MFU) by chip.
How the model is built.
Every SKU is counted twice, from opposite ends of the supply chain.
-
Supply view
Total potential units, built up from capacity orders: foundry wafer starts, 2.5D packaging bookings, and HBM build plans.
-
Demand view
Actual shipments by SKU and quarter, tracked independently of what the capacity implies.
-
Reconciliation
The two views are reconciled into shipments, installed base, and FLOPS. The gap between them is where constraints show up first.
Research that ships with the model.
Model subscribers receive the update notes, webinars, and analysis published against each release. A sample of recent coverage:
Common questions.
Anything not covered here, ask the team directly through the form below.
What does the Accelerator & HBM Model include?
Five reconciled modules: accelerator shipments, ASPs, and specifications by SKU, optical engine and co-packaged optics attach, supply chain and capacity orders, HBM and memory tracking, and customer-level installed base with FLOPS. Forecasts run to 2030 with history back to 2021, on a quarterly basis.
How is the model delivered?
As an Excel workbook with dashboard access for your team.
Is it part of the SemiAnalysis newsletter subscription?
No. Industry models are separate institutional offerings and are not included with the annual newsletter membership.
Can the data estimate supplier revenue?
Yes. Because production is built up from equipment requirements, wafer starts, and packaging orders, revenue for many upstream and downstream companies can be estimated directly from the data.
Models that pair with this one.
Pairing depends on the decision in front of you. The SKU-level build here feeds SKU and non-SKU versions of the models around it.
AI Networking Model
Spend forecastSizing the cluster networking spend that scales with every accelerator deployment: switches, transceivers, and scale-up fabrics.
View model
AI Cloud TCO Model
Cost modelTurning deployed accelerators into rental economics and total cost of ownership across AI clouds.
View model
Memory Model
Supply & pricingFollowing the DRAM and NAND supply, demand, and pricing behind the HBM attach.
View modelGet the Accelerator & HBM Model.
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- Scoped to your use case
- Dashboard and API access for your team
- Custom research engagements available
