Memory Model
Bottoms-up analysis of the global DRAM and NAND markets, from the fab floor to the spot market: wafer capacity by fab, bit supply and demand, contract pricing, and HBM by generation and supplier, quarterly, with DRAM through 2030 and NAND through 2027.
- Markets
- 3 tracked
- Vendors
- 9 covered
- Forecasts
- Through 2030
- Cadence
- Quarterly
A bottoms-up model of the memory market.
The SemiAnalysis Memory Model tracks the global DRAM and NAND flash markets from the fab floor to the spot market. Installed wafer capacity and utilization by fab, node and layer transitions, die-level yield analysis, and bits per wafer build the supply side; shipment tracking across servers, mobile, PCs, and consumer categories builds demand.
On top of the balance sit contract pricing with forecasts, HBM pricing and shipments by generation and supplier, vendor margins from die-level cost modeling, and a DRAM and NAND capex tracker. Quarterly data runs from 2022, through 2030 for DRAM and 2027 for NAND.
Who uses it, and what it decides.
The buyers of this model, and the calls they make with it.
- Institutional investors
- Positioning through the memory cycle with the quarterly supply-demand balance, inventory correction tracking, and pricing forecasts underneath the vendor prints.
- Hyperscalers & data center buyers
- Purchase timing and supply risk for DRAM, NAND, and HBM: when the balance tightens, what pricing does next, and which vendors have the bits.
- Consumer OEMs & ODMs
- Supply chain planning for mobile, PC, and tablet memory: demand by end market, contract pricing direction, and shortage risk by product class.
- Semiconductor companies
- Competitive analysis at the fab level: capacity, node and layer migrations, yield positions, and capex plans for every major and emerging memory maker.
From wafer starts to price forecasts.
Supply is built fab by fab, demand market by market, and pricing sits on the balance between them.
The supply side, fab by fab
Installed capacity and technology migrations set what the industry can ship:
Capacity & utilization
Installed monthly wafer capacity and actual utilization by fab, vendor, and technology node
Node & layer transitions
DRAM migrations across 1α, 1β, and 1γ, and NAND layer counts from 176L to 300L and beyond
HBM & SOCAMM supply
HBM and SOCAMM output tracked in both wafers and bits, alongside the commodity supply
From wafers to bits
Die-level analysis turns wafer capacity into the bit supply that actually clears the market:
Die & yield analysis
Die size and density by node and vendor, gross die per wafer, net good die, and mature and ramping yield curves
Bits per wafer
Bits per wafer for each process node from each memory company, adjusted for node and layer transitions
Bit supply by vendor
Total bit supply and annualized bit growth, by vendor and at the fab level, with quarterly granularity
Demand and pricing
The demand side and the prices that clear it, history and forecast:
Bits demand
Demand estimates from shipment and growth tracking across servers, mobile, tablets, PCs, and laptops
Contract pricing
Historical and forecasted contract pricing for major commodity and premium memory products
HBM pricing
HBM pricing across generations and suppliers, with shipments in stacks, bits, and wafers, aligned with the Accelerator Model
The economics, priced from the die
Vendor gross margins by process node and product segment, built from die-level cost modeling and observed ASPs, sit alongside predictive supply-demand analysis, inventory correction cycles, shortage risk, and a DRAM and NAND capex tracker with segmental analysis of capacity growth and infrastructure roadmaps.
The memory cycle.
Memory is the most cyclical market in semiconductors. Supply decisions made at the peak arrive in the trough, and the model tracks every quarter of the loop: capacity, bits, inventory, and price.
Phase 01 · Tightening
Demand catches supply
Inventories drain, spot prices cross above contract, and buyers stretch their order books. The turn shows up in the quarterly balance before it shows up in vendor results.
In the model: quarterly bit supply against bit demand by end market, inventory correction tracking, and contract price history
Phase 02 · Peak pricing
Margins peak, capex follows
Shortage pricing fattens gross margins and finances the next wave of capacity. Every vendor adds wafers into the strongest quarters, and the seeds of the downturn are planted at the top.
In the model: pricing forecasts by product, vendor margins by node from die-level cost modeling, and the DRAM and NAND capex tracker
Phase 03 · Oversupply
The bits arrive together
New capacity lands while node shrinks and layer adds raise bits per wafer, so supply grows faster than the market ordered it. Prices roll over from the top of the stack down.
In the model: wafer capacity and utilization by fab, bits per wafer by node and layer count, and annualized bit growth by vendor
Phase 04 · Correction
Cuts clear the market
Utilization falls, capex slips to the right, and inventory burns down until the balance tightens again. Positioning for the next phase depends on reading this one correctly.
In the model: utilization by fab and vendor, capex by segment, and the supply-demand balance that times the turn
Diagram of the memory market cycle as a loop: tightening leads to peak pricing, peak pricing to oversupply, oversupply to correction, and correction back to tightening. Selecting a phase shows its description.
The dial is the shape of the market, not a market call. The workbook carries the quarterly numbers behind each phase: supply, demand, inventory, and price from 2022, through 2030 for DRAM and 2027 for NAND.
How the model is built.
Fabs first, bits second, and the price set by the balance.
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Start from the fabs
Installed monthly wafer capacity and actual utilization by fab, vendor, and node, with technology transitions tracked as they ramp: DRAM node migrations and NAND layer count moves.
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Convert wafers to bits
Die size and density, gross and net good die, and yield curves turn wafer starts into bits per wafer and vendor bit supply. Demand is built independently from shipments across end markets.
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Price the balance
Supply against demand drives the pricing model: contract price history with forward price forecasts, HBM pricing aligned with the Accelerator Model, and margins checked against vendor results every quarter.
Research that ships with the model.
Model subscribers receive the update notes, webinars, and analysis published against each release. A sample of recent coverage:
Common questions.
Anything not covered here, ask the team directly through the form below.
What does the Memory Model include?
Installed wafer capacity and utilization by fab, vendor, and node, DRAM node transitions across 1α, 1β, and 1γ, NAND layer counts from 176L to 300L and beyond, die size and yield analysis with gross and net good die, bits per wafer, bit supply and demand by vendor and end market, contract pricing with forecasts, HBM pricing and shipments by generation and supplier, vendor margins from die-level cost modeling, and a DRAM and NAND capex tracker. Quarterly data runs from 2022, through 2030 for DRAM and 2027 for NAND.
Which memory vendors does it cover?
All major and emerging vendors. For DRAM: Samsung, SK Hynix, Micron, CXMT, Nanya Tech, Winbond, JHICC, and YMTC. For NAND: Samsung, SK Hynix including Solidigm, Kioxia-Sandisk, Micron, and YMTC.
How deep is the HBM coverage?
HBM pricing across multiple generations and suppliers, both backward- and forward-looking, paired with vendor-level shipment volumes expressed in stacks, bits, and wafers, plus HBM and SOCAMM supply tracked in wafers and bits. The analysis is aligned with the SemiAnalysis Accelerator Model and its global AI accelerator shipment data.
How is the model delivered?
As an Excel model with quarterly data from 2022, through 2030 for DRAM and 2027 for NAND, one year of quarterly updates with additional features and enhancements, an initial onboarding call on the model structure and methodologies, ongoing ad-hoc support calls, and timely updates from the lead analyst on key industry developments.
Is it part of the SemiAnalysis newsletter subscription?
No. Industry models are separate institutional offerings and are not included with the annual newsletter membership.
Models that pair with this one.
Memory feeds the accelerators, the tools build the fabs, and logic rides the same equipment cycle. The other models cover each link.
Accelerator & HBM Model
The HBM demandWhere the HBM stacks go: accelerator shipments SKU by SKU, the demand side of the pricing this model carries.
View model
Wafer Fab Equipment Model
The toolsThe equipment side of the capex this model tracks: tool demand across five segments, DRAM and NAND included.
View model
Foundry Industry Model
The logic fabsThe other half of the wafer market: shipments, capacity, and pricing across 19 logic foundries.
View modelGet the Memory Model.
Start with the sales team. They come back with scoping, licensing, and pricing for your mandate.
- Scoped to your use case
- Onboarding and ad-hoc analyst calls included
- Custom research engagements available
