Newsletter

SemiAnalysis STEEL

Teardown Engineering and Evaluation Lab

A teardown lab, from product to transistor.

SemiAnalysis STEEL is an 18,000 square foot teardown engineering and evaluation lab in Hillsboro, Oregon. Boards, packages, dies, and interconnects are taken apart, imaged, and measured here by a team with more than 90 years of combined failure-analysis experience.

Commission a teardown See the capabilities

Or inquire about our teardown products.

Top-down photograph of a Huawei Ascend 910C accelerator board with two large dies at its centre and rows of components around them Opened Apple M5 Max package showing a blue logic die between four memory stacks, with epoxy residue around the edges Underside of a ball-grid-array package under an optical microscope, solder balls in rings around the centre with a one millimetre scale bar Polished cross-section of a small chip on a circuit board, two pale copper features under a thin die on a dark background
Huawei Ascend 910C accelerator board Optical, board overview

What only a teardown can tell you.

Datasheets and benchmarks stop at what a vendor chooses to publish and what a workload happens to exercise. Physical analysis measures the part itself: which fab and node it came from, how it is packaged, what the process looks like, and what it costs to make.

Teardown labs are capital and staff intensive, and the United States has lacked a domestic resource for independent semiconductor competitive analysis. SemiAnalysis is funding one now, while experienced failure-analysis engineers are available and domestic semiconductor suppliers are expanding.

What datasheets, benchmarks, and the lab can each tell you
Information Datasheets Benchmarks STEEL What it decides
Fab and node verification No No Direct and detailed Export-control violations and the response to them
Architecture details General Indirect Direct and detailed Capability benchmarking
Advanced packaging specifics General No Direct and detailed Monitoring and responding to PRC advances
Process reverse engineering No No Direct and detailed IP discovery
Manufacturing cost estimation No No Detailed estimate Component costing
Custom process variations No No Direct, with advanced analysis Monitoring and responding to PRC advances
Circuit schematics, partial or full No No Direct, via extraction IP discovery

How a part comes apart.

Every part follows the same path, from non-destructive imaging to a written report. Once the die is exposed, the four analysis branches run in parallel.

  1. 01 Non-destructive analysis X-ray, macro optical
  2. 02 Disassembly and package analysis X-ray, macro, micro
  3. 03 Decapsulation and die exposure Prep labs
  • Die imaging Prep labs, optical, SEM
  • Critical dimensions, materials characterization, fab sourcing Optical, FIB, SEM, TEM
  • Delayering and inspection Prep labs, FIB, SEM
  • Circuit extraction and cost analysis Architecture, BoMs
  • Comprehensive reporting Strategic prioritization
  • Transistor and functional-unit electrical analysis Planned

Prep and analysis under one roof.

Sample preparation and the analytical instruments sit in the same facility, with a short list of techniques nearsourced or planned.

Preparation

  • Delid and detach
  • Laser decapsulation
  • Wet and dry etch
  • Mechanical polishing Parallel, cross-section, wedge, dimpling, CNC
  • FIB and plasma FIB XSEM, XTEM, PSEM, PTEM; delayering and packaging
  • Ion etch and ion milling

Analysis

  • Macro imaging
  • Compound optical and fluorescence
  • X-ray Sub-micron CT and laminography
  • SEM and SEM-EDS
  • TEM and STEM
  • Aberration-corrected STEM With EDS

Nearsourced and planned

  • Femtosecond laser Cross-section and delayering
  • LSM
  • CSAM
  • Nanoprobing
  • Dry etch
  • EELS, SIMS, XPS, XRF Chemical and composition analysis
Polished cross-section through a package substrate: pale copper layers, vias, and solder joints on a dark field
Grey electron-microscope image of a cross-section, a cluster of round filler particles beside stacked metal layers
Blue-tinted optical image of a die surface with a dense grid of bumps and a darker block to one side
Optical image of a blue package sitting among rows of small components on a circuit board
X-ray computed-tomography rendering of solder balls glowing white against black
Optical image of a die in purple tones covered in a regular array of bumps with several rectangular blocks
Polished cross-section of a board with a die on top, thin copper traces, and three large plated vias beneath
Two opened processor packages resting on a black tray under warm light

Selected optical, X-ray, and electron-microscope images from the lab.

On the bench.

Recent work from the lab, and what is in the queue.

Optical microscope view of a green interposer surface with fine wiring and small pads Interposer, optical, after delayering

Apple M5 Pro and Max: Fusion architecture

Apple’s first use of TSMC’s SoIC-mH 2.5D packaging. The CPU and GPU are separate dies, bonded copper to copper onto the interposer through a hybrid bonding interface, and the interposer carries features that only delayering exposes.

Close-up of a small blue chip with an Apple logo and part markings on its lid Apple IVR, package marking

Apple M5 Max: integrated voltage regulator

Apple’s IVR chip sits on the back of the logic board and holds a constant, stable voltage for the CPU and GPU. Located on the board, delidded, and cut in cross-section.

Top-down photograph of the Ascend 910C accelerator board Accelerator board, optical

Huawei Ascend 910C: advanced packaging

Polished cross-section and 2D X-ray of the full package: ABF build-up layers, PCB build-up, memory-stack TSVs, and GPU microbumps, with pitch, critical dimensions, and floorplan measured.

Blue-tinted view of a phone logic board, two camera modules at the top and shielded blocks of components below Phone logic board

Kirin 9030 Pro: iPoP architecture

Package-on-package with an organic interposer. X-ray identified the memory substrate supplier and likely heat-management structures.

What a report looks like

Two STEEL teardowns published on the SemiAnalysis newsletter.

Intel Panther Lake Teardown Looking inside Intel 18A and Panther Lake: backside power, gate-all-around transistors, and Foveros-S. A free STEEL teardown. By Adith Shankar Read the report Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s? A deep dive on SMIC’s N+3 node against TSMC N6: process technology, patterning, and cell architecture, from the Kirin 9030. By the STEEL team Read the report

In the queue

  • Exynos 2600
  • Apple M5 series
  • Ascend 910C
  • Advanced optics products
  • Advanced networking products
  • Advanced datacenter ICs

The first teardown reports are out. The lab is open to suggestions and commissions.

18,000 square feet in Hillsboro.

The lab sits in Hillsboro’s Amberglen district, on the same streets as the Hillsboro sites of Intel, Lam Research, KLA, Nvidia, ASM, and Applied Materials.

  • Full-featured preparation and analytical labs
  • Room to bring new capabilities in quickly
  • Space for collaborators and affiliates

9025 NE Von Neumann Drive
Hillsboro, OR 97006
Open in Maps

Photographs from inside the STEEL lab: benches, microscopes, sample-preparation tools, and the SemiAnalysis sign at the entrance Photographs from inside the STEEL lab: benches, microscopes, sample-preparation tools, and the SemiAnalysis sign at the entrance

Commission a teardown.

Tell us the part and the question. The sales team comes back with scope, timing, and pricing.

  • Teardown reports, published from Q3 2026
  • Commissioned teardowns and custom analysis
  • Suggestions for the queue welcome

The lab is hiring product, architecture, packaging, and technician roles. See the open roles

Tell us what you are trying to find out. The sales team will follow up to scope the work and provide pricing.

← Back

Thank you for your response. ✨